Due to the large dynamic range of the human auditory system, and the ability of logarithmic systems to encode sounds efficiently, logarithmic µ-law speech encoding has been used in digital telephone system CODECs for some time. However, no presently available processor is capable of directly processing the compressed samples. We have developed an FIR filter circuit that provides for two identical 32-tap log-encoded filters, has programmable coefficients, and operates at a 12.5 kHz sampling rate. The circuit has been designed to operate on simple log encoded data. The chip is comprised of a systolic array of eight logarithmic multiplier accumulator circuits and is consequently called the SALMA-8. As the eventual application of this chip is a programmable digital hearing aid, we have designed for low power dissipation and small area. Power consumption is minimized while maintaining a wide dynamic range through the use of sign/logarithm arithmetic[1]. Power dissipation is a mere 1.2 mW, and the die is 5.7 by 5.3 mm. Four of the SALMA-8 chips, a logarithmic ADC, and a logarithmic DAC, have been combined to implement a four-channel digital hearing aid. In this paper we will discuss the architecture of the filter chip, describe its performance in the combined system, and illustrate its eventual application in a digital hearing aid.

As illustrated in Figure 1, the SALMA-8 is comprised of a linear array of eight cells. Each of these processing units, called the multiplexed logarithmic multiply accumulator cell (MLMAC), is capable of performing eight logarithmic multiply-accumulate operations and is responsible for performing four taps in each of two separate filters. A complete filter operation requires the SALMA-8 array to be used four times. The first cycle has only the sampled data as an input and generates a partial sum output. This partial sum is then used as input during the second cycle which uses different data and coefficients. This pattern continues until completion of the fourth cycle which generates the final filter output. The process is then repeated with a separate set of data to implement a second, identical filter.

The MLMAC, shown in Figure 2, consists of eight sampled data registers, two coefficient registers,and a logarithmic multiplier-accumulator unit. The eight sampled data registers are divided into two separate chains of shift registers which operate in opposite directions. The first chain is used for sampled data associated with the first N/2 filter coefficients, while the second chain's data are used with the remaining coefficients. This structure exploits the symmetry of the filter response, which is a consequence of the fact that the filters are constrained to be linear phase. Each data value passes through a given MLMAC twice, traveling in opposite directions. In this way, the first and last sampled data values appear in the same MLMAC simultaneously and will use the same coefficient. Similarly, sample number i and sample N-i (for a length N+1 filter) will appear in the same cell and use the same coefficient. By having the data flow in this manner, it is possible to halve the number of registers required to store the filter coefficients.

As can be seen in Figure 2, only four of the eight registers are available to the data multiplexer at any one time. The data values for the two separate filters are interleaved; thus, only the data for one of the filters is available at any given time. Four cycles, corresponding to each of the four available data values, are required for a complete filter operation. After a filter operation is completed, the data is shifted so as to make the second filter's data available, and the second filtering operation is performed.

Each MLMAC also consists of a logarithmic ALU which performs the required multiply-accumulate operations on data in sign/logarithm format. The multiply operation is performed by a full adder, as multiplication of two numbers simply becomes addition when sign/logarithm arithmetic is involved; however, addition of two sign/logarithm numbers requires the use of a lookup table. If the sum X+Y is evaluated as X(1+Y/X), one finds that the 1+Y/X term may be evaluated by a lookup table. The table is efficiently implemented as a programmable logic array, because fewer than 25% of the table entries are non-zero[2]. With an eight bit data word composed of a sign bit and seven log-magnitude bits, it is possible to achieve a dynamic range in excess of 100 dB and an RMS SNR of 31 dB. Because of the logarithmic nature of the number system, the SNR is constant and independent of the signal's magnitude or frequency spectrum, provided the the signal remains within the dynamic range of the system[3].

Both the MLMAC and SALMA-8 circuits have been fabricated through MOSIS using a 3µ CMOS process. The 20,000 transistor SALMA-8, pictured in Figure 3, is 30.2 mm2 and has a measured power consumption of 1.2 mW at 5 V and a 12.5 kHz sampling rate. The MLMAC has a measured propagation delay on the order of 100 nS. It should be noted that emphasis was placed on obtaining low power consumption at the expense of speed. More extensive use of dynamic logic and the introduction of pipelining into the logarithmic ALU could dramatically increase the MLMAC's maximum speed of operation

The SALMA-8 will be incorporated into a four channel digital hearing aid (Figure 4), in which the audio spectrum is divided into four mutually exclusive frequency bands between 200 Hz and 6 kHz[4]. Each channel consists of a pre-filter, followed by a gain and hard limit stage. The post-filter, whose response is identical to the pre-filter, is used to remove the out of band harmonic distortion introduced by the hard limit operation. In the near future, all four filter channels along with the control, gain, and limit stages will be implemented on a single die. Also, the logarithmic ADC and logarithmic DAC circuits, with the corresponding anti-aliasing filters will be implemented on a second chip. This two chip set will be able to operate from a conventional hearing aid battery and will consume less than 2 mW of power.

Four SALMA-8 chips have been incorporated into a bench-top, programmable, four channel, audio signal processing system as illustrated in figure 5. The four SALMA-8 chips receive their data and much of their control from the Digital Hearing Aid Breadboard (DHAB), a TMS32010 based multiprocessor signal processor[5]. The system also includes a logarithmic ADC and logarithmic DAC which are presently board level designs, soon to be implemented in VLSI. The DHAB obtains the logarithmically encoded data from the ADC and passes it directly to the four SALMA-8 chips where the data is passed through the pre-filter of each of the four channels. The DHAB then captures the filters' outputs, introduces a gain to each of the four channels, performs a limit operation, and passes each of the four intermediate values to the appropriate SALMA-8 for the post-filter operation. Finally, the DHAB retrieves the post-filters' outputs, combines them into a single value, and passes this result to the DAC which expands the data and passes the analog signal to the output transducer. The DHAB receives the filter coefficients and gain values from a host system and loads them into the SALMA-8 via a serial communications link.

All of the filters tested to date exhibit performance consistent with theory. Examination of the frequency response of the logarithmic filters implemented reveals filter transfer functions which deviate only slightly from responses obtained from equivalent filters implemented with conventional fixed-point arithmetic. Qualitatively, the results are equally encouraging; however further study is necessary.

[1] N.G. Kinsbury and P.J. Rayner, "Digital Filtering Using Logarithmic Arithmetic," Electronic Letters, 7, pp. 56-58, 1971.

[2] J.H. Lang, C.A. Zukowski, R.O. LaMaire, and C.H. An, "Integrated Circuit Logarithmic Arithmetic Units," Massachusetts Institute of Tech. Report, EE and CS Department, 1983.

[3] A.D. Edgar and S.C. Lee, "FOCUS Microcomputer Number System," Communications of the ACM, 22(3), March 1979.

[4] R.E. Morley, Jr., G.L. Engel, T.J. Sullivan, and S.M. Natarajan, "VLSI Based Design of a Battery-Operated Digital Hearing Aid," ICASSP-88 Proceedings, pp. 2512-2515, April 1988.

[5] R E. Morley, Jr., A. Maynard Engebreston, and Joseph G. Trotta, "A Multiprocessor Digital Signal Processing System for Real-Time Audio Applications," IEEE Transactions on Acoustics, Speech, and Signal Processing, January 1986.