Electronic Systems and Signals Research Laboratory

Washington University in Saint Louis

Department of Electrical Engineering

Saint Louis, MO 63130

While the natural world in which we live is filled with analog signals, the world of modern integrated circuit design is dominated by digital technology. In many applications digital signal processing (DSP) with its many advantages is an attractive alternative to traditional analog signal processing. DSP offers flexibility, ease of programmability, stability, and a growing list of other benefits.

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At present the cost of designing analog circuits in terms of both time and money is high, and so the preferred strategy is to perform as much processing as possible in the digital domain where processors can be developed quickly and produced in high volumes at low cost. This approach allows products to change rapidly in response to ever-changing market demands. While technological progress always makes it necessary to re-evaluate how tasks are distributed between the digital and analog domains, the trend toward performing more processing in the digital domain is likely to continue.

Concurrently, the task of designing analog circuits for signal conditioning, acquisition, and reconstruction of the digital data has never been more exciting. Many signal processing applications, especially in the biomedical area, are requiring analog interfaces with increased performance at lower supply voltages while consuming less power to supply data to a new generation of low-power, low-voltage, special-purpose digital signal processors. There are many applications in speech processing which might benefit from advances in low-power digital signal processing.

For example, a digital hearing aid capable of providing improved performance over any presently available analog device might be realizable [1]. Conventional analog hearing aids offer limited performance and are difficult to adjust properly for a given patient. Furthermore, due to mechanical vibration and shock, as well as component aging, their characteristics are known to deviate from their original setting, causing the fit to be altered. While digital signal processing with its renown for long-term stability, ease of programmability, et cetera has as yet not been incorporated into ear-level hearing aid designs, significant progress towards achieving this goal has been reported.

In particular, at the previous workshop held in Monterey a small, low-power FIR filter circuit that provides for two identical 32-tap logarithmically encoded filters, has programmable coefficients, operates at a 16 kHz sampling rate, and intended for use in a programmable digital hearing aid was described [2]. In this sequel we present the design of an experimental analog interface processor, also intended for use in the proposed digital hearing aid, with emphasis directed toward both the theoretical and practical issues concerning the design of efficient, low-power data converters employing sign/logarithm encoding.

The choice of digital representation of analog waveforms plays a major role in determining both the complexity and power consumption of the integrated circuits used to acquire, process, and reconstruct the digital data. Commonly, µ-law compression characteristics are used in voiceband applications to attain an economical data representation while not interfering with speech perception [3]. However, if signal processing functions, most of which involve linear operations, are to be performed directly on the digital signals then it has been necessary, before processing, to convert the compressed data into a linear format.

In a filter employing linear arithmetic in which the digital representation is directly proportional to the amplitude of the signal, the relative accuracy with which a signal can be represented depends on its magnitude. Unfortunately, one of the principal factors governing the power consumption of a digital filter is the word length. For small word length, the dynamic range as well as the signal-to-noise ratio of the filter is severely limited if a linear representation is used. An alternate method of computation uses numbers proportional to the logarithm of the signal amplitude.

Sign/logarithm [4, 5] arithmetic is especially well-suited to a digital hearing aid application, fulfilling the requirements for wide dynamic range, small word size, and adequate signal-to-noise ratio. Others have demonstrated that logarithmic number systems give filtering performance superior to that of a floating point number system of equivalent word length and dynamic range [6]. The logarithmic data representation permits data compression without compromising the fidelity of the signals while at the same time reducing the power consumption and size of the integrated circuits dramatically. For example, logarithmic multiply-accumulate cells occupy roughly one-third the area of their equivalent fixed-point counterparts [7].

In sign/logarithm arithmetic multiplication becomes simple addition, and addition can be performed by evaluating

X + Y = X   (1)

log = log + log . (2)

A table lookup may be used to evaluate the log (1 + Y/X) term. In the logarithmic domain, the multiply-accumulate operation can be accomplished very efficiently with the equivalent of only four eight-bit additions and a table lookup. Moreover, the lookup table is sparse and can be efficiently implemented as a programmable logic array (PLA).

d < x(n)  d . (3)

-  < x(n)  -  . (4)

After the quantization stage, the quantized sample must be represented by a code word c(n). The code word used to encode a sample which is contained in the ith quantization level is simply the integer, i, representing the log magnitude of the input sample, along with one additional bit used to encode the polarity of the input. Hence, small values of i encode large signal amplitudes.

The dynamic range afforded by the quantization method is important. Sign/logarithm encoding provides large dynamic range with a relatively small number of bits. The dynamic range, DR, is given by

DR(dB) = - 20 log10   (5)

where N is the total number of bits in the representation. The value N includes the "sign" bit. The dynamic range dependence upon logarithm base for several values of N is illustrated in Figure 1.

Figure 1: Dynamic Range Dependence Upon Logarithm Base and Word Length

Moreover, adequate RMS signal to RMS quantizing noise ratios are achievable provided the logarithm base is chosen near unity. Under some simplifying assumptions one may show that [7]

SNR(dB) = 20 log10  . (6)

Equation (6) is plotted in Figure 2.

Figure 2: RMS Signal-to-Quantizing Noise Dependence Upon Logarithm Base

In particular, (6) assumes an infinite number of quantization states as well as placing some restrictions upon the statistics of the input signal. It is possible, however, to show that for a finite number of quantization intervals and a Laplacian distribution of input amplitudes, often used to model speech, and for a sufficiently large number of states with a logarithm base near unity the signal-to-noise ratio is given by

SNR(dB) = -10 log10   (7)

Thus, by choosing an appropriate logarithm base and a sufficiently large number of quantization states the sign/logarithm encoding scheme offers performance very close to that afforded by commercial codecs as demonstrated in Figure 3.

Figure 3: Comparison of Sign/logarithm and µ255-Law Quantizing Noise

Finally, in the design of sign/logarithm quantizers it is important to consider the distortion introduced into an overall system when different subsystems are operating with logarithm bases which differ slightly from one another. For example, how will system performance be degraded if an analog voltage is sampled with a quantizer operating with a logarithm base, d1, but then reconstructed with a base, d2? Moreover, in the proposed digital hearing aid application, mismatches between the input quantizer and internal lookup tables of the logarithmic signal processor as well as between these tables and the output decoder are likely to occur. A Fourier analysis reveals that the residual nonlinearity as a result of the mismatch will generate harmonic terms which lie below the distortion introduced by the quantization process itself provided the mismatch in logarithm bases is not greater than 0.25%. Consequently, any proposed conversion scheme must be capable of establishing the logarithm base with a high degree of accuracy.

While much time and effort have been devoted to the study and design of linear data converters, little or no attention has been given to the design of converters with logarithmic characteristics other than the A- or µ-law companding converters used by the telecom industry. Only one family of commercial DACs with exponential characteristics similar to those described above is presently available. The Analog Devices converter AD7111, however, employs a 17-bit R-2R CMOS multiplying DAC with extensive digital input logic. The digital logic merely translates the 8-bit binary input into a 17-bit linear word which is used to drive the multiplying DAC. Hence, while the AD7111 is by function a "logarithmic DAC", it is in design simply a linear data converter. Furthermore, no commercial logarithmic ADC which produces output words in sign/logarithm format exists.

Data conversion circuits are best realized using CMOS whenever low power consumption is important. The ability to fabricate high-performance, high-density capacitors has lead to a plethora of charge-redistribution techniques in recent years. All of these schemes possess the property that circuit operation is determined by capacitor ratios which can be set with accuracies approaching 0.1% rather than by an inexact RC product. The importance of accurately setting the logarithm base was established in the previous section. Therefore, an important premise in the proposed conversion algorithms is their reliance upon switched-capacitor (SC) techniques to ensure great accuracy.

Although the characteristics of RC circuits are studied in elementary courses on electronics, the potential of RC circuits to perform logarithmic conversions has seemingly in large part been dismissed or overlooked [8]. The parallel RC circuit of Figure 4a can be quickly transformed to the SC equivalent of Figure 4b by replacing the resistor Rs by its parallel SC equivalent. In the circuit of Figure 4b, logarithmically encoded data is converted to an analog voltage by first precharging master capacitor, Cm, to a reference voltage, Vref, while slave capacitor, Cs, is discharged to ground through switch S3. The polarity of the reference voltage is controlled by the sign bit of the logarithmically encoded digital word.

Figure 4: Switched-Capacitor Equivalent of Parallel RC Circuit

v =  Vref . (8)

v =  v =  Vref . (9)

The process is continued for n clock cycles where n is the digital encoding of the log magnitude of the output sample. The voltage across the master capacitor is then given by

v =  Vref where r =  . (10)

Finally, defining

d =   (11)

we write

v = dn Vref . (12)

Note, the logarithm base, d, is not a function of the absolute value of either capacitor; but rather, it depends only upon an highly accurate capacitor ratio, r.

Sensitivity of the logarithm base to the inevitable errors associated with the capacitor ratio is an important measure of performance. As previously stated, it is important that any proposed method of conversion ensure an accurate determination of the logarithm base. This fact raises the obvious question: how sensitive is the logarithm base, d, to the capacitor ratio, r, for the circuit of Figure 4a? Relative sensitivity of a function, d, due to a parameter, r, is defined as

S =  =  . (13)

A relative error in the logarithm base, d, is then related to a relative error in the capacitor ratio, r, in the following manner

 = S . (14)

Taking the partial derivative of (13) using (11), one finds

S =  = (r + 1)  =  . (15)

By using (11) it is possible to express the relative sensitivity directly in terms of the logarithm base, d, in which case

S = 1 - d. (16)

We conclude that the logarithm base is indeed very insensitive to capacitor ratio errors for values of d greater than 0.9, and hence with typical capacitor ratio errors of less than one percent it is not difficult to establish the log base with an accuracy of better than 0.25 percent as prescribed in the previous section.

Unfortunately, the serial nature of this simplistic approach to logarithmic conversion makes the process inherently slow. More than 150 switch closures are required to obtain a modest dynamic range of 85 dB. It is possible, however, to modify the algorithm for converting log-encoded data to an analog voltage so that all conversions can be performed with at most 10 switch closures.

Encoding an analog voltage in a logarithmic format is in principle quite simple. A switched-capacitor equivalent of a parallel RC circuit, i.e. the circuit of Figure 4b, is used to generate an exponentially decaying voltage across a capacitor. This voltage is then compared to a sampled input and the number of charge redistribution cycles tallied until the capacitor voltage decays to a value equal to or less than the sample and held input. Naively, we can envision an analog comparator signaling the above inequality and, in turn, freezing the counter output which monitors the number of redistribution cycles. Another comparator would determine the polarity of the sample. The counter output along with this sign bit then serves as the logarithmic representation of the analog voltage.

In practice, however, the task is quite difficult. The major problems associated with this direct implementation described above are the very small step-sizes encountered (a few µV) when converting low-level input signals and the inherent slowness of a serial A/D conversion technique. The design of a comparator (especially in low-voltage, low-power design environments) capable of resolving small voltage differences in a short period of time is an extremely difficult, if not impossible, task. However, if one is clever this impediment to good performance can be overcome.

In order to demonstrate the usefulness of the proposed sign/logarithm encoding scheme in voiceband application an experimental analog interface processor (AIP) for use in a digital hearing aid will be briefly described. A block diagram of the processor is illustrated in Figure 5. Input signals originating at the microphone must first be amplified by a low-noise preamplifier and then bandlimited. The analog-to-digital converter provides logarithmically encoded data at a 16 kHz rate to its companion chip, a custom digital signal processor capable of performing operations directly on the log-encoded data. In order to reduce the number of interconnects, data is transferred between chips in a serial fashion.

The digital signal processor, after processing this data as per the hearing aid specifications, returns the filter results to the AIP where the data is then converted back to an analog voltage by the logarithmic digital-to-analog converter. After additional signal conditioning, a class D power amplifier excites the output transducer. Moreover, voltage multipliers for increasing the total supply voltage and an oscillator for generating clock pulses, as well as control logic and reference circuitry, reside on the AIP microchip.

Figure 5: System Overview of Analog Interface Processor

A low-power analog data interface intended for use in a digital hearing aid to supply logarithmically encoded data to a special-purpose low-power digital signal processor is currently under development. The use of sign/logarithm encoding results in substantial savings in both power and area of the integrated circuits. Moreover, if an appropriate logarithm base and word length are chosen sign/logarithm quantizers can provide performance, with respect to both noise and dynamic range, which is nearly identical to the performance afforded by more traditional µ-law compandors. The proposed integrated circuit logarithmic analog-to-digital and digital-to-analog converters rely heavily upon switched-capacitor charge redistribution techniques in order to achieve high accuracy and low power.