Lab Exercise 1 : Using
Design Architect To Capture a VLSI Design
Lab Exercise 2 : Functional
Simulation with QuickSim II
Lab Exercise 3 : Functional
Simulation with AccuSim II
Lab Exercise 4 : Schematic
Driven Layout Using IC Station
Lab Exercise 5 : IC
Extraction and Backannotation
Lab Exercise 6 : Hierarchical
Designs with SDL
Lab Exercise 7 : Functional
Simulational with Lsim
Lab Exercise 8 : Creating
Designs And Ics Using Verilog HDL
APPENDIX : Advanced
Schematic Driven Layout