INTRODUCTION TO VHDL MODELING AND SIMULATIONS USING DESIGN ARCHITECT AND QVPRO

1. INTRODUCTION

This tutorial gives a step-by-step introduction to VHDL modeling and simulations in Mentor Graphics.

1.1 About VHDL:

VHDL+ is a hardware description language intended for documenting and modeling digital systems ranging from a small chip to a large system. IEEE selected and approved an IEEE standard called IEEE Std 1076-1987 for VHDL. After a number of clarifications and addition of new features, IEEE revised the standard to IEEE Std 1076-1993.

1.2 Modeling:

VHDL provides five kinds of design units to model a design (or a circuit), of which the following three are of primary interest:

An entity declaration describes the interface of the design to its external environment, that is, it describes the ports (inputs, outputs, etc.) through which the design communicates with other designs.

An architecture declaration describes the composition or functionality of a design. This could be described as a mix of sequential behavior, concurrent behavior, and components. A design may have more than one architecture body, each describing a different composition, that is, using a different style of design. Fig. 1 shows such a scenario.

An entity declaration and one architecture body defines a design entity. See Fig. 2 . Note that a number of design entities can be created using the same entity declaration. For example, to represent a 1-bit full-adder with an entity declaration, there may be three architecture bodies - one that describes the behavior of the full-adder, another architecture body that describes the full-adder as a netlist of simple gates from a library such as AND and OR gates, and a third architecture body describing the full-adder using half-adders.

A configuration declaration is used to specify the bindings of components present in an architecture body to other design entities. An entity hierarchy of a design, that is, the bindings that link all the design entities in a hierarchy, can also be specified using the configuration declaration.

NOTE : + VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

1.3 Directories and their Organization:

VHDL modeling (particularly in the Mentor Graphics environment) requires proper organization of directories. Typical directory structure is shown in Fig. 3 (directories are shown as ellipses while files are shown as rectangular boxes).

quickvhdl.ini :

src :

vhdl_lib :

symbol :

component :

2. GETTING STARTED WITH VHDL MODELING:

(1) In order to access Mentor Graphics' tools, the following path has to be set up in your .cshrc.user file in the set path command:

/opt/apps1/mgc/bin \

Also, the following environment variables have to be set in your .cshrc.user file in your home directory.

NOTE: If you have already inserted the above, ignore the environment and path set ups.

(2) In order to access Mentor Graphics' VHDL functions and utilities, the following environment variables have to be set in your .cshrc file in your home directory.

(3) Source your .cshrc file using the command source .cshrc at the command prompt.

4) Next, you have to create vhdl and its subdirectories in EE483 directory. So, change your current working directory to EE483 by typing cd EE483 at the command prompt and press Return. Under EE483 directory , create vhdl subdirectory using mkdir vhdl command. Then, change directory to vhdl to create src, symbol and component subdirectories (use mkdir command). DO NOT WORRY ABOUT THE vhdl_lib SUBDIRECTORY FOR THE TIME BEING.

5) Invoke Design Architect from the same shell ( from /home/username/EE483/vhdl by typing da .

(6) Using OPEN VHDL icon in the session_palette , open a dialog box as shown in Fig.4 . You will be using this dialog box for declaring entity and architecture.

(7) Expand the Options by selecting YES and fill the form as shown in Fig. 4 and click on OK .

(8) In the VHDL editor, enter the following entity ( mux_e ) declaration and save it using the pull-down File > Save .

(9) Close the window by double-clicking on the window bar shown in Fig. 5 .

(10) Follow the steps (6) through (9) to declare the following architecture for the multiplexer ( mux_a ) in the src directory.

11) Now you're ready to define the working library viz. vhdl_lib . Using the pull-down QuickVHDL > Lib... qvlib (make sure there is nothing active in the work area i.e. none of the editors like VHDL editor, symbol editor, schematic editor etc should be open, otherwise the QuickVHDL pull-down will not show up in the pull-down), open the dialog box shown in Fig. 6 . Fill up the box as shown and click on OK .

The following message ( Fig. 7 ) will appear in the message area. Ignore the message for the time being.

(12) After creating the design library (the above step defines the physical location of the working library), a logical mapping of the library has to be done. This can be done by using the pull-down QuickVHDL > Map... qvmap . Fill the dialog box as shown in Fig. 8 . Make sure you select the Set button before entering the logical and physical name. The logical name is the same as physical map name here, but they need not be the same. The qvmap modifies the quickvhdl.ini file created in the vhdl directory.

(13) Now you can compile your code. Using the pull-down QuickVHDL > Compile... qvcom , open the dialog box shown in Fig. 9 . Enter the File Name as shown in Fig. 9 .

Click on Options... to open the options.

The options entries are shown in Fig. 10 . . Set the options as shown in Fig. 10 and click on OK . Click on OK in the qvcom dialog box.

(14) The compilation message(s) appear in the Transcript window. To see the window, use the pull-down MGC > Transcript > Show Transcript . Use the scroll bars to scroll down. If there are any errors, the errors will be listed. If errors do show up, go back to the VHDL editor and fix the errors and use qvcom to compile the declaration again. You cannot simulate your code until it compiles successfully.

(15) Repeat steps (13) and (14) on the architecture declaration mux_a.

(16) Close all windows in the Design Architect work area (do not close Design Architect ).

(17) Now you are ready to generate the symbol. Design Architect defines the symbol based on the information that you give in the Generate Symbol dialog box.Note that the figure has been split for convenience. Using the pull-down File > Generate > Symbol... , open the dialog box shown in Fig. 11 . Follow the directions given in the figure and click on Choose Shape . This opens a form containing various shapes. Click on Trapezoid and click on OK . Close the Generate Symbol dialog box by clicking on OK . A symbol opens up in the Symbol Editor with properties attached to it.

(18) Check the symbol using the pull-down Check > With Defaults . There should not be any errors. Save the symbol using the pull-down File > Save Symbol . Fig. 11: Generate Symbol dialog box(please note that the box has been split for convenience)

(19) Next, you have to instantiate the symbol using the schematic editor . Use the OPEN SHEET icon in the session_palette to open a schematic edit session for the multiplexer. In the Open Sheet dialog box, use Navigator button or enter the following in the Component Name field:

Use the Options field if you want to add sheet borders. Close the form by clicking on OK .

(20) Using the CHOOSE SYMBOL palette icon, place the generated mux8 symbol in the schematic editor. Add portins and portout as shown in Fig. 12 . Make sure to use ADD BUS to connect the nets.

(21) Check the symbol using the pull-down Check > Sheet . Correct errors, if any.

(22) Save the schematic using the pull-down File > Save Sheet .

(23) Exit Design Architect .

(24) Now you're ready to invoke the simulator. At the command prompt type pwd to ensure that you're in /home/username/EE483/vhdl directory . If not, change directory to the vhdl subdirectory in EE483 directory.

(25) Type the following and press return at the command prompt:

This invokes the simulator ( qvpro ) on your mux8_schem in the component directory using the entity and architectures created (by Mentor Graphics) in the vhdl_lib working library.

(26) Note that there are two windows invoked by the simulator - one is QVPro (QuickVHDL) window and the other is QVPro (QuickSim II) window. The former is used for running qvsim simulations while the latter is used for running QuickSim II simulations. We would be using the latter for our simulations.

(27) In the QVPro (QuickSim II) window (which is very much similar to the QuickSim II window) , open the sheet by clicking the palette item Open Sheet .

(28) Enter the following forces using the Add Force icon in the STIMULUS palette as shown in TABLE 1 .

29) Open the Trace window and run the simulation for 700ns .

(30) Verify whether the circuit behaves the way it should.

(31) Save the set up using the pull-down menu File > Save > Setup... . In the Pathname , enter /home/username/EE483/vhdl/component/mux8_schem/qvpro_setup and click on OK .

(32) Exit the simulator.

3. MIXED DESIGN TECHNIQUES

The following steps will take you through the design and simulations of mixed components i.e. VHDL counter model and 74ls161A from TTL library.

1. Using the techniques described earlier, enter the following entity ( counter_e ) and architecture ( counter_a ) declarations ( Fig. 13a and Fig. 13b respectively) for a 4 bit counter in the src subdirectory in the vhdl directory.

2. Define working library as vhdl_lib and map it as you did before.

3. Using qvcom compile your entity and architecture declarations.

4. Generate symbol for the 4 bit counter and place it in the symbol directory. Check the symbol and save it.

5. Open Schematic Editor and enter the schematic shown in Fig. 13 in the name mixed_counter in the component directory.

6. Using palette item CHOOSE SYMBOL , place the counter_4bit symbol in the schematic area.

7. From the ls_lib choose 74ls161a component and place it in the schematic.

8. Add 8x1 rip from the gen_lib and define an 8-bit wide bus IN(7:0) such that the input A of the 74ls161a is the LSB while the input d of the counter_4bit is the MSB. Label the rips.

9. Complete the circuit by adding portins, portouts, vcc and ground from the gen_lib .

10. Check the schematic using the pull-down Check > Sheet and correct errors, if any.

11. Save the schematic using the pull-down File > Save Sheet and exit Design Architect .

12. From the same shell (ensure the working directory is /home/username/EE483/vhdl ) invoke qvpro simulator on the schematic mixed_counter .

YOUR ASSIGNMENT:

Simulate and annotate the Trace or List window on the above circuit for the following values. Use the 74LS161A data sheet and the behavioral description of the vhdl model and write a brief report on the functioning of the circuit.