Bradley L. Noble

Degrees

D.Sc. Electrical Engineering, Washington University
St. Louis MO, August 2000
Dissertation: ``Algorithms and Performance Analysis for Speculative Computation in Discrete-Event Simulation''

M.S. Electrical Engineering, Southern Illinois University
Edwardsville, March 1992
Thesis: ``A Study of the Two-Dimensional Wavelet Transform''

B.S. Electrical Engineering, Southern Illinois University
Edwardsville, May 1990

Professional Experience

Associate Professor, Southern Illinois University Edwardsville,
Department of Electrical and Computer Engineering,
August 2004 to present.

Assistant Professor, Southern Illinois University Edwardsville,
Department of Electrical and Computer Engineering,
September 2000 to July 2004.

Instructor, Southern Illinois University Edwardsville,
Department of Electrical and Computer Engineering,
August 1996 to August 2000.

Research Assistant, Washington University, St. Louis, MO
Computer and Communications Research Center,
January 1994 to July 1996.

Network Engineer, Systems Engineering Solutions Incorporated, St. Louis, MO,
March 1995 to August 1996.

Teaching Assistant, Southern Illinois University Edwardsville,
Department of Electrical Engineering,
January 1990 to December 1991.

Computer Programmer and Operator, Sachs Electric Company, St. Louis, MO,
June 1985 to December 1989.

Honors and Awards

``Best Paper in the Software Technology Track'' - 32nd Hawaii Internation Conference on System Sciences, January 1999

First Place Poster Award - 1995 Graduate Student Research Fair, School of Engineering, Washington University

Outstanding Paper and Presentation Award - American Society for Engineering Education (ASEE) Conference, Notre Dame University

Member, Eta Kappa Nu Engineering Honor Society
National Collegiate Engeering Award, 1990

Publications

A. G. Lozowski and B. L. Noble. Processing temporal sequences. Proceedings of the Midwest Symposium on Circuits and Systems (MWSCAS'02), (Tulsa, Oklahoma), Aug. 4-7, 2002.

B. L. Noble and R. D. Chamberlain. Analytic Performance Model for Speculative, Synchronous, Discrete-Event Simulation. Proceedings of the 14th Workshop on Parallel and Distributed Simulation, May 2000.

B. L. Noble and R. D. Chamberlain. Performance Model for Speculative Simulation Using Predictive Optimism. Proceedings of the 32nd Hawaii International Conference on System Sciences, January 1999.

B. L. Noble and R. D. Chamberlain. Performance of Speculative Computation in Synchronous Parallel Discrete-Event Simulation on Multiuser Execution Platforms. Proceedings of the 8th IASTED International Conference on Parallel and Distributed Computing and Systems, October 1996.

Y. Chen, B. L. Noble and R. D. Chamberlain. Comparing Edge-cuts to Communications Volume in Parallel VLSI Logic Simulation. Proceedings of the 8th IASTED International Conference on Parallel and Distributed Computing and Systems, October 1996.

B. L. Noble and R. D. Chamberlain. Predicting the Future: Resource Requirements and Predictive Optimism. Proceedings of the 9th Workshop on Parallel and Distributed Simulation, June 1995.

B. L. Noble, G. D. Peterson, and R. D. Chamberlain. Performance of Synchronous Parallel Discrete-Event Simulation. Proceedings of the 28th Hawaii International Conference on System Sciences, January 1995.

B. L. Noble, G. D. Peterson, and R. D. Chamberlain. Performance of a Synchronous Parallel Simulator. PVM Users' Group Meeting, May 1994.

A. Godhwani and B. L. Noble. A Motorola 56001 Code Generator for Plant Simulation. ASEE Conference, March 1992.

O. Alkin and B. L. Noble. CSS: A Tool for Time-Domain Simulations of Systems International Conference on Simulation and Engineering Education, January 1992.


URL: http://www.ee.siue.edu/~bnoble/vitae/
Created by: bnoble@ee.siue.edu
Last update: Thu Jun 2 15:48:21 CDT 2005