"Performance Predictions for Speculative, Synchronous, VLSI Logic
Simulation," Bradley L. Noble, J. Cris Wade, and Roger D. Chamberlain,
In Proceedings of the 34th Annual Simulation Symposium, April 2001, pp. 56-64.
"Analytic Performance Model for Speculative, Synchronous, Discrete-Event Simulation," B.L. Noble and R.D. Chamberlain,
In Proceedings of 14th Workshop on Parallel and Distributed Simulation, June 2000.
"Performance Model for Speculative Simulation Using Predictive Optimism." B.L. Noble and R.D. Chamberlain,
In Proceedings of 32nd Hawaii International Conference on System Sciences, January 1999. Awarded Best Paper in Software Technology Track.
"Performance of Speculative Computation in Synchronous Parallel Discrete-Event Simulation on Multiuser Execution Platforms."
Bradley L. Noble and Roger D. Chamberlain,
In Proceedings of the 8th IASTED Internation Conference on Parallel
and Distributed Computing and Systems (PDCS'96).
Chicago, IL, October 1996.
"Comparing Edge-cuts to Communications Volume in Parallel VLSI Logic Simulation."
Yuhua Chen, Bradley L. Noble and Roger D. Chamberlain,
In Proceedings of the 8th IASTED Internation Conference on Parallel
and Distributed Computing and Systems (PDCS'96).
Chicago, IL, October 1996.
"Predicting the Future: Resource Requirements and Predictive Optimism,"
Bradley L. Noble and Roger D. Chamberlain.
In Proceedings of the 9th Workshop on Parallel and Distributed Simulation
(PADS'95).
Lake Placid, NY, June 1995.
"Performance of Synchronous Parallel Discrete-Event Simulation."
Bradley L. Noble, Gregory D. Peterson, and Roger D. Chamberlain,
In 28th Hawaii International Conference on System Sciences.
Waileau, Maui, HI, January 1995.
"Performance of a Synchronous Parallel Simulator."
Bradley L. Noble, Gregory D. Peterson, and Roger D. Chamberlain,
PVM Users' Group Meeting May 1994. Oak Ridge, TN.